Semiconductor Integrated Circuits (IC) are increasingly more complex with millions of devices such as transistors connected together to perform intended functions. An IC may be created by a design process performed by a design house, followed by a fabrication process performed by a dedicated fab company.
An IC design process may start with a software description, e.g., in a programming language such as C or VHDL, of the functionality of the circuit, which is then synthesized to interconnected gate-level hardware elements. Next the hardware elements and their connections are physically laid out, represented as placements of geometric shapes, often referred to as a layout, on a variety of layers to be fabricated on the semiconductor device. Afterwards, the IC design together with the description of the IC layout, is transferred to an IC fabrication facility for fabrication.
IC layouts may be created by a computer aided design (CAD) tool or an electronic design automation (EDA) tool and stored in a database, and may undergo a number of modifications before the final fabrication. For example, a design house may separate one IC design into several smaller layouts for design parallelism, and those smaller layouts will need to be assembled together to form the original circuit for fabrication.
A layout-versus-layout (LVL) comparison, or layout verification, of two IC layouts is essential to ensure that an original layout of an IC represents the same circuit after it has gone through a modification process to become a second layout. LVL comparison may detect the differences between two layouts, often by performing a Boolean exclusive-or (XOR) operation of the two layouts. Traditionally, performing XOR of two layouts needs to use the EDA tools that created the layout.
With the ever increasing integration of semiconductor systems, IC designs and IC layouts have become increasingly complex. Data files associated with IC layout descriptions have become larger as well. These larger files consume more computing resources and are more difficult to perform XOR of two layouts for LVL comparison. Therefore, there is a need for methods and systems for performing LVL comparison more efficiently.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.